VeroTherm FAR XP

Our VeroTherm FAR XP system offers high precision and tunable process control, ensuring superior yield performance with bumps as small as 7 µm tall at 12 µm pitch.

Our unique single-step process offers high throughput with no defects and a minimal inter-metallic zone of less than 1 µm.

This process is qualified at the world’s largest IDM & HBM manufacturers, guaranteeing industry-leading reliability and efficiency.

Wafers

Runs two wafer sizes in parallel in large batch sizes.

Panels

Handles panel dimensions down to 200 μm thickness without breakage.

Copper Eless

Efficient electroless plating of copper for both surface bonding and glass core liner.

Values

Optimal on-board chemical
management

Specialized handling with panel shock

Low COO with high throughput

Applications

Via liner

Build-up layers

Interconnects

Glass Etch

Tested on multiple commercially available substrates, the glass core etch can be specified for specific glass needs.

Values

Specialized glass panel handling

Optimized chemical usage

Onboard analysis and metrology

Applications

Through glass via etch

Glass cavity etch for embedded devices

ENEPIG / ENIG

Electroless plating processes for enhanced bonding in advanced packaging.

Values

Optimal on-board chemical management

Specialized handling with panel shock

Low COO with high throughput

Applications

Final layer interface for bonding

Extends package lifetime

Protects copper layers from oxidation

Metal Etch

Metal etch capability for Cu, Ti, TiW, Ru, and more.

Values

Multiple chemical processes available

Efficient onboard chemical management

Chemical cabinets available
for bulk chemical delivery

Applications

Seed metal etch

Standard Cleans

Metal etch capability for Cu, Ti, TiW, Ru, and more.

Values

High efficiency processing

Ultrasonic and megasonic agitation available

Flexible setup for multiple processes

Applications

Front end particle cleans

Post SiC wafer cleans

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Values

High yield reflow performance

Single wafer vacuum reflow architecture enables excellent process sensitivity and control.

Lower cost of ownership

Single step process enables high throughput with high yield and a small footprint.

Technology
extendibility

Able to process 7 µm bump at 12 µm pitch.

Applications

Solder Reflow – C4 bumps, Cu pillar

Chip-to-wafer and wafer-to-wafer bonding reflow

Thin die stacking reflow

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