VeroFlex FAR PLP
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General information
VeroFlex FAR PLP is a fluxless formic acid reflow system for high-quality defect free, void free reflow performance.
Single substrate architecture designed to enable process sensitivity extendible to ultra-low fine pitch micro bumps.
Multi-generational system with ability to process substrates from 50 x 50 mm to 650 x 650 mm.
Datasheet & Specs
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Values
Vacuum process
Achieve superior reflow performance with high yield and void prevention, ensuring a smooth bump surface with a high-quality soak
Single panel architecture
Controls sidewall wicking with very low IMZ; prevents Sn/Ag agglomerates
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IR heating mechanism
High yield with superior thermal uniformity, even for warped panels
Applications
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Chip-on-wafer bonding
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Flip-chip chip-scale package bonding
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Solder bump and Cu pillar reflow
Other products
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