VeroFlex FAR PLP

VeroFlex FAR PLP is a fluxless formic acid reflow system for high-quality defect free, void free reflow performance.

Single substrate architecture designed to enable process sensitivity extendible to ultra-low fine pitch micro bumps.

Multi-generational system with ability to process substrates from 50 x 50 mm to 650 x 650 mm.

Wafers

Runs two wafer sizes in parallel in large batch sizes.

Panels

Handles panel dimensions down to 200 μm thickness without breakage.

Copper Eless

Efficient electroless plating of copper for both surface bonding and glass core liner.

Values

Optimal on-board chemical
management

Specialized handling with panel shock

Low COO with high throughput

Applications

Via liner

Build-up layers

Interconnects

Glass Etch

Tested on multiple commercially available substrates, the glass core etch can be specified for specific glass needs.

Values

Specialized glass panel handling

Optimized chemical usage

Onboard analysis and metrology

Applications

Through glass via etch

Glass cavity etch for embedded devices

ENEPIG / ENIG

Electroless plating processes for enhanced bonding in advanced packaging.

Values

Optimal on-board chemical management

Specialized handling with panel shock

Low COO with high throughput

Applications

Final layer interface for bonding

Extends package lifetime

Protects copper layers from oxidation

Metal Etch

Metal etch capability for Cu, Ti, TiW, Ru, and more.

Values

Multiple chemical processes available

Efficient onboard chemical management

Chemical cabinets available
for bulk chemical delivery

Applications

Seed metal etch

Standard Cleans

Metal etch capability for Cu, Ti, TiW, Ru, and more.

Values

High efficiency processing

Ultrasonic and megasonic agitation available

Flexible setup for multiple processes

Applications

Front end particle cleans

Post SiC wafer cleans

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Values

Vacuum process

Achieve superior reflow performance with high yield and void prevention, ensuring a smooth bump surface with a high-quality soak

Single panel architecture

Controls sidewall wicking with very low IMZ; prevents Sn/Ag agglomerates

IR heating mechanism

High yield with superior thermal uniformity, even for warped panels

Applications

Chip-on-wafer bonding

Flip-chip chip-scale package bonding

Solder bump and Cu pillar reflow

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